// SPDX-License-Identifier: (GPL-2.0+ or MIT)
/* Copyright(c) 2020 - 2023 Allwinner Technology Co.,Ltd. All rights reserved. */
/*
 * Copyright (C) 2023 panzhijian@allwinnertech.com
 */

#ifndef _DT_BINDINGS_CLK_SUN55IW6_H_
#define _DT_BINDINGS_CLK_SUN55IW6_H_

#define CLK_PLL_DDR		0
#define CLK_PLL_PERI0_PARENT	1
#define CLK_PLL_PERI0_2X	2
#define CLK_PERI0_DIV3		3
#define CLK_PLL_PERI0_800M	4
#define CLK_PLL_PERI0_480M	5
#define CLK_PLL_PERI0_600M	6
#define CLK_PLL_PERI0_400M	7
#define CLK_PLL_PERI0_300M	8
#define CLK_PLL_PERI0_200M	9
#define CLK_PLL_PERI0_160M	10
#define CLK_PLL_PERI0_16M	11
#define CLK_PLL_PERI0_150M	12
#define CLK_PLL_PERI0_25M	13
#define CLK_PLL_PERI1_PARENT	14
#define CLK_PLL_PERI1_2X	15
#define CLK_PLL_PERI1_800M	16
#define CLK_PLL_PERI1_480M	17
#define CLK_PLL_PERI1_600M	18
#define CLK_PLL_PERI1_400M	19
#define CLK_PLL_PERI1_300M	20
#define CLK_PLL_PERI1_200M	21
#define CLK_PLL_PERI1_160M	22
#define CLK_PLL_PERI1_150M	23
#define CLK_PLL_VIDEO0_4X	24
#define CLK_PLL_VIDEO1_4X	25
#define CLK_PLL_VE		26
#define CLK_PLL_NPU_4X		27
#define CLK_AHB			28
#define CLK_APB0		29
#define CLK_APB1		30
#define CLK_APB_UART		31
#define CLK_TRACE		32
#define CLK_GIC			33
#define CLK_ITS0_ACLK		34
#define CLK_ITS0_HCLK		35
#define CLK_NSI			36
#define CLK_NSI_CFG		37
#define CLK_MBUS		38
#define CLK_IOMMU		39
#define CLK_GMAC1_MBUS_GATE	40
#define CLK_GMAC0_MBUS_GATE	41
#define CLK_ISP_MBUS_GATE	42
#define CLK_CSI_MBUS_GATE	43
#define CLK_NAND_MBUS_GATE	44
#define CLK_DMA1_MBUS_GATE	45
#define CLK_CE_MBUS_GATE	46
#define CLK_VE_MBUS_GATE	47
#define CLK_DMA0_MBUS_GATE	48
#define CLK_DMA0		49
#define CLK_DMA1		50
#define CLK_SPINLOCK		51
#define CLK_MSGBOX0		52
#define CLK_MSGBOX_CORE0	53
#define CLK_MSGBOX_CORE1	54
#define CLK_MSGBOX_CORE2	55
#define CLK_MSGBOX_CORE3	56
#define CLK_MSGBOX_RV		57
#define CLK_PWM0		58
#define CLK_PWM1		59
#define CLK_PWM2		60
#define CLK_DBGSYS		61
#define CLK_SYSDAP		62
#define CLK_TIMER0		63
#define CLK_TIMER1		64
#define CLK_TIMER2		65
#define CLK_TIMER3		66
#define CLK_TIMER4		67
#define CLK_TIMER5		68
#define CLK_TIMER6		69
#define CLK_TIMER7		70
#define CLK_BUS_TIMER		71
#define CLK_TIMER0_RV		72
#define CLK_TIMER1_RV		73
#define CLK_TIMER2_RV		74
#define CLK_TIMER3_RV		75
#define CLK_RV_BUS_TIMER	76
#define CLK_DE			77
#define CLK_DE0			78
#define CLK_G2D			79
#define CLK_BUS_G2D		80
#define CLK_VE			81
#define CLK_BUS_VE		82
#define CLK_CE			83
#define CLK_CE_SYS		84
#define CLK_BUS_CE		85
#define CLK_NPU			86
#define CLK_NPU_TZMA		87
#define CLK_BUS_NPU		88
#define CLK_RV_CORE		89
#define CLK_RV_TS		90
#define CLK_RV_CFG		91
#define CLK_DRAM		92
#define CLK_BUS_DRAM		93
#define CLK_NAND0		94
#define CLK_NAND0_CLK2X		95
#define CLK_BUS_NAND0		96
#define CLK_SMHC0		97
#define CLK_BUS_SMHC0		98
#define CLK_SMHC1		99
#define CLK_BUS_SMHC1		100
#define CLK_SMHC2		101
#define CLK_BUS_SMHC2		102
#define CLK_BUS_UART0		103
#define CLK_BUS_UART1		104
#define CLK_BUS_UART2		105
#define CLK_BUS_UART3		106
#define CLK_BUS_UART4		107
#define CLK_BUS_UART5		108
#define CLK_BUS_UART6		109
#define CLK_BUS_UART7		110
#define CLK_BUS_UART8		111
#define CLK_BUS_UART9		112
#define CLK_BUS_UART10		113
#define CLK_BUS_UART11		114
#define CLK_BUS_UART12		115
#define CLK_BUS_UART13		116
#define CLK_BUS_UART14		117
#define CLK_TWI0		118
#define CLK_TWI1		119
#define CLK_TWI2		120
#define CLK_TWI3		121
#define CLK_TWI4		122
#define CLK_TWI5		123
#define CLK_TWI6		124
#define CLK_SPI0		125
#define CLK_BUS_SPI0		126
#define CLK_SPI1		127
#define CLK_BUS_SPI1		128
#define CLK_SPI2		129
#define CLK_BUS_SPI2		130
#define CLK_SPIF		131
#define CLK_BUS_SPIF		132
#define CLK_SPI3		133
#define CLK_BUS_SPI3		134
#define CLK_SPI4		135
#define CLK_BUS_SPI4		136
#define CLK_GPADC0		137
#define CLK_BUS_GPADC0		138
#define CLK_GPADC1		139
#define CLK_BUS_GPADC1		140
#define CLK_GPADC2		141
#define CLK_BUS_GPADC2		142
#define CLK_GPADC3		143
#define CLK_BUS_GPADC3		144
#define CLK_THS			145
#define CLK_IRRX0		146
#define CLK_BUS_IRRX0		147
#define CLK_IRTX		148
#define CLK_BUS_IRTX		149
#define CLK_LRADC		150
#define CLK_TPADC_24M		151
#define CLK_TPADC		152
#define CLK_LBC			153
#define CLK_LBC_NSI_AHB		154
#define CLK_BUS_LBC		155
#define CLK_IRRX1		156
#define CLK_BUS_IRRX1		157
#define CLK_IRRX2		158
#define CLK_BUS_IRRX2		159
#define CLK_IRRX3		160
#define CLK_BUS_IRRX3		161
#define CLK_I2SPCM0		162
#define CLK_BUS_I2SPCM0		163
#define CLK_I2SPCM1		164
#define CLK_BUS_I2SPCM1		165
#define CLK_I2SPCM2		166
#define CLK_BUS_I2SPCM2		167
#define CLK_I2SPCM3		168
#define CLK_BUS_I2SPCM3		169
#define CLK_OWA_TX		170
#define CLK_OWA_RX		171
#define CLK_OWA			172
#define CLK_DMIC		173
#define CLK_BUS_DMIC		174
#define CLK_AUDIO_CODEC_DAC_1X	175
#define CLK_AUDIO_CODEC		176
#define CLK_USB			177
#define CLK_USB20_0_DEVICE	178
#define CLK_USB20_0_HOST_EHCI	179
#define CLK_USB20_0_HOST_OHCI	180
#define CLK_USB1		181
#define CLK_USB20_1_HOST_EHCI	182
#define CLK_USB20_1_HOST_OHCI	183
#define CLK_USB2_REF		184
#define CLK_USB2_SUSPEND	185
#define CLK_USB3_REF		186
#define CLK_USB30		187
#define CLK_PCIE_REF_AUX	188
#define CLK_PCIE_SLV		189
#define CLK_SERDES_PHY_CFG	190
#define CLK_SERDES_PHY_REF	191
#define CLK_SERDES_AXI		192
#define CLK_GMAC0_PHY		193
#define CLK_GMAC0_PTP		194
#define CLK_GMAC0		195
#define CLK_GMAC1_PHY		196
#define CLK_GMAC1_PTP		197
#define CLK_GMAC1		198
#define CLK_GMAC_NSI		199
#define CLK_VO0_TCONLCD0	200
#define CLK_BUS_VO0_TCONLCD0	201
#define CLK_DSI0		202
#define CLK_BUS_DSI0		203
#define CLK_VO0_COMBPHY0	204
#define CLK_DPSS		205
#define CLK_LEDC		206
#define CLK_BUS_LEDC		207
#define CLK_CSI_MASTER0		208
#define CLK_CSI_MASTER1		209
#define CLK_CSI_MASTER2		210
#define CLK_CSI_MASTER3		211
#define CLK_CSI			212
#define CLK_BUS_CSI		213
#define CLK_ISP			214
#define CLK_BUS_ISP		215

#endif /* _DT_BINDINGS_CLK_SUN55IW6_H_ */
